In 1965, Gordon Moore’s bold prediction set the pace for the modern world of electronics. Over five decades ago, he projected that dramatic increases in computing power and decreases in relative cost would occur at an inconceivable rate. Since the establishment of Moore’s Law, computer power has -- as predicted -- doubled every 18 months. Today, some artificial intelligence (AI) experts believe the next computing evolution will deliver technology smart enough to understand its own designs and self-direct exponential improvements.
The rise of AI, like most preceding disruptive technologies, has invigorated the semiconductor industry, driving global growth across multiple applications within diverse market sectors. Five years ago, AI was a wild ambition; more hype than reality. Now, the nearly 60 percent of people in the world connected to the Internet are already using AI technology that’s built into smartphones and smart wireless devices.
As AI and the Internet of Things (IoT) converge, the growth of AI devices will surge, delivering new technologies in smart transportation, smart homes and smart sensors for more integrated, intelligent devices. Currently, AI is one of the major growth engines for the electronics industry, with sensors as the key enablers for smart functionality and semiconductor advances the linchpin for sensor capability. In fact, the SEMI industry association is forecasting that AI and the 5G cellular communication standard will be major growth drivers pushing the semiconductor market to over US $500 Bn by the year 2020. And the market has capitalized on the opportunities this expansion presents, as evidenced by the rise in new chip startups and venture capitalist (VC) funding. Last year, VCs invested more than US $1.5 Bn in emerging AI chip companies.
AI’s growth has the realization of Moore’s Law to thank; the technology is possible due to the shrinking size of transistors – a footprint reduction that has occurred steadily over the past five decades. With consumers demanding smaller, more capable and increasingly connected devices, semiconductor packages have followed suit with the development of system-in-package (SiP) and multi-functional devices, initially placing die side-by-side or stacked, moving to three-dimensional (3D-IC) integration.
While some experts are predicting the end to significant transistor scaling by 2020, noting that integrated circuits (IC) cannot get much smaller as transistors are already approaching the size of an atom, innovation will march on. The proliferation of 3D-IC packaging and smarter software ensure continued advancements in the semiconductor industry.
Device miniaturization will persist, even though the pace may slow. With ongoing dimensional reductions comes greater integration at the package level and accompanying design and reliability challenges. In addition to shrinking device footprints and thicknesses, it’s common that ICs with higher and lower operating frequencies are contained in a singular semiconductor package, as is the case with some SiP devices. RF isolation of single-package, varying-frequency ICs is one of the newer 3D-IC integration challenges. Because conventional EMI shielding caps do not comply with the required super-thin packaging dimensions or protect against in-package interference, novel isolation techniques and conductive adhesives are being used as alternative approaches to traditional EMI shielding.
Moving from 2D-IC designs to 2.5D or 3D-ICs, packaging engineers are facing a major paradigm shift. The dimensional challenges associated with this transition are many, not the least of which is the requirement to control the thermal load. As the 3D silicon structure is relatively immature, reliability data is somewhat sparse. Ongoing 3D integration including 3D-IC and 3D silicon integration must address the reliability considerations for heat dissipation over smaller areas.
To enable 3D silicon integration, material specialists have developed wafer-level underfill films for stacked silicon ICs and micro-bump bonding, which are integrated between the IC and organic substrate. Adhesives designed to help reduce warpage, particularly for stacked package applications used in through-silicon-via (TSV) devices, are also making new designs possible.
Small handheld and wearable devices are fueling a large part of the growth for multi-functional 3D SiP packages. As a case-in-point, Apple’s first iPhone in 2007 had two wafer-level packages (WLP). By 2016, the iPhone 8 plus design contained 60 WLPs (59 fan-in and 1 fan-out) and the Apple Watch launched using 0.35 mm-pitch WLCSPs coated with an EMI shielding material.
On an almost daily basis, Moore's Law, smart computing and AI innovations are being increasingly integrated into our lives and our dependence upon them is becoming more pronounced. Consumers will continue to demand incremental increases in capability, placing new challenges on semiconductor packaging engineers.
At some point in the future, intelligent computers may help semiconductor packaging engineers overcome these challenges, develop next- generation semiconductor devices, resolve 3D-IC design constraints and pre-empt unforeseen reliability issues. For now, though, packaging engineers will have to face these obstacles while pushing the limits of physics with shrinking IC packaging designs.
Doug Dixon heads business development initiatives at 360Biz, a B2B Marketing and Technology agency that helps clients generate leads and sales through advanced, personalized websites. We work with a diverse client base in various industries including semiconductor manufacturing and electronics assembly.